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Highlights from ARM TechCon 2010

November 11th, 2010 | Posted by thomas in Latest News

We were at the ARM TechCon yesterday, the yearly Woodstock for ARM-lovers. This article details news from NXP, IAR and Micrium which caught our attention.

 


 

 

 

 

NXP Semiconductors is coming out with a single-chip dual-core micro-controller, its LCP4xxx series. While it was announced a few weeks ago, NXP gave a 1-hour seminar on how it actually works. it’s a Cortex-M4, coupled with a Cortex-M0. Each core can be programmed and debugged separately, but share everything on the chip (i.e. both can access all peripherals).

In NXP’s mind, one would you use the Cortex-M4 much like a DSP, e.g. spending all of its computation power crunching numbers. NXP showed a demonstration where the Cortex-M4 does audio processing while the Cortex-M0 communicates with a computer. The Cortex-M0 is used for “administrative” tasks, i.e. I/O to the peripherals, and, in the WSN case, networking. Of course, both cores can be switched to low-power modes independently.

The LPC4xxx has been announced, and is coming out in steps. The first ones (end 2010) will have no RAM/flash (the idea is to hook up external chips), then other will be released with up to 1MB flash and 512kB RAM in 2011.

 

IAR gave a very convincing set of tutorials on the trace capabilities of their Integrated Development Environment. Trace is the creme-de-la-creme of debugging tool, in which a debug probe connects to the ETM module inside the Cortex-M3/M4, and receives every program counter in real-time, without having to pause the micro-controller. In a wireless mote, you do not want to pause the micro-controller, as the radio chip goes on doing its thing, and when you reactivate the micro-controller, they are out of sync.

In its simple usage, Trace enables advanced source code profiling: if shows how often the micro-controller executes a function, what percentage of CPU cycles is consumed by each function, a graphical timeline of the sequence of interrupts, a graphical timeline of which function is called, etc. This requires a micro-controller with an ETM module (many Cortex-M3/M4 chips have it; it can not be added to a Cortex-M0) and a specific debug probe. From IAR, it’s called J-Link Trace.

IAR also showed a demo of their latest technology, power debugging. The idea is to monitor the current consumption of the chip/board, and correlate that with the program counter obtained through Trace, to see which function consumes what amount of energy. IAR is the only company to provide this capability, for now.

You need a specific debug probe called IAR J-Link Ultra; the consumption data integrates nicely into the IDE, appearing as an extra bar-graph in the “trace” timelines. Note that the J-Link Ultra does not implement “full” trace (connecting to the ETM module) but rather “single-wire” trace which outputs only every 64th program counter.

IAR confirmed that a “full” trace version of their J-Link Ultra is on their way. Future revisions of the product will increase time and current measurement resolutions. Note that this technology assumes that the board is powered through the debug probe. IAR is also working on a analog extension to the debug probe which you can connect to shunt resistors you have put on your board, allowing you to monitor the consumption of individual chips. We expect this will be announced at the 2011 Embedded Systems Conference.

 

Micrium confirmed that they are working on an IPv6-enables version of uC/TCP-IP, but it remains unclear when it will be commercially available (tentatively in 6 to 12 months).

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